The accuracy of duty cycles of a clock of an electronic device with high frequency interfaces, like a DDR-SDRAM interface, is very important. Typically, the duty cycle of the clock is carefully considered during the design of an integrated circuit or an electronic device. Furthermore, the duty cycle of the clock may also be verified by simulations. However, due to variations in the manufacturing process some discrepancies may be present for different electronic devices or integrated circuits. Due to these discrepancies, the interfaces may not be able to operate as fast as designed, (e.g. because of variations of the duty cycle) which could lead to a loss in the overall performance of the device.
FIG. 1 shows a schematic representation of a communication between an integrated circuit IC and an external memory DDR or an external device according to the prior art. While the integrated circuit IC is designed to generate a clock CLK, a clock CLK1 different from the designed clock CLK is transmitted via an interface to the external memory DDR. The deviations in the clock signals may be due to variations in the manufacturing process of the integrated circuit.
US Patent Publication No. 20040189364 A1 (published Sep. 30, 2004) titled, “Integrated Circuit Devices having Improved Duty Cycle Correction and Methods of Operating the Same,” of Woo-Jin Lee, et al., discloses an integrated circuit with a duty city correction. Here, a duty cycle correction of high speed interfaces like a DDR interface is described. However, the solution described in this document relates to an analogue solution. Due to an analogue solution, drift between samples may cause serious problems.